The present invention relates to an active matrix cell driven by a thin-film field effect transistor (to be referred to as a TFT hereinafter) used in a liquid crystal display, and a method of manufacturing the active matrix cell.
A liquid crystal display (LCD) using a liquid crystal as a display medium has been studied and developed in place of a CRT display since the LCD has a small depth and low power consumption and is compact as compared with the CRT display, and some liquid crystal display models are popular in practical applications. In recent years, an active matrix type liquid crystal display has received a great deal of attention. In this active matrix type liquid crystal display, TFTs are arranged in each pixel to drive the pixel.
A typical active matrix type liquid crystal display has a structure wherein a liquid crystal is sandwiched between an active matrix substrate having TFTs thereon and a counter substrate, an entire surface of which receives a uniform potential. Basic units (pixels) consisting of TFTs and pixel electrodes are arranged on the active matrix substrate in a matrix form. Scanning lines for controlling the TFTs and data lines for supplying data to the pixel electrodes are arranged in a matrix form along the X and Y directions. On a discussion of an active matrix substrate, only a repetition unit including parts of data and scanning lines 1 and 2, a TFT 3, and a pixel electrode 4, as shown in FIG. 7, can be taken into consideration to grasp the entire structure of the active matrix substrate. The repetition unit is defined as an active matrix cell herein. Referring to FIG. 7, reference numeral 5 denotes a source of the TFT 3; 6, a drain of the TFT 3; 7, an intersection region between the data and scanning lines 1 and 2. It should be noted that the drain and source of a general TFT are not discriminated from each other.
Since an active matrix substrate having TFTs formed thereon is used in an active matrix type liquid crystal display, the fabrication process is more complex than a simple multiplex type liquid crystal display in which a liquid crystal is sandwiched between an X-direction wiring substrate and a Y-direction wiring substrate. Therefore, the product yield of the active matrix type displays is undesirably decreased, and it is difficult to provide a high-quality large display at low cost. Various attempts have been made to decrease the number of steps in manufacturing the active matrix substrate. The process is often evaluated by the number of photomasks (to be referred to as masks hereinafter). Active matrix substrate manufacturing processes from which manufacturing steps are reduced are called two- and three-mask processes, which are reported as transactions and the like. The number of masks under discussion is the number required for manufacturing the active matrix substrate. Therefore, masks required for forming an alignment layer are excluded from the number of masks.
A conventional active matrix substrate manufacturing method from which the manufacturing steps are reduced will be described below. The scanning and data lines are indispensable elements in the active matrix substrate. Therefore, two masks for the scanning and data lines cannot be eliminated.
The two-mask process is described in "AN IMPROVED DESIGN OF ACTIVE MATRIX LCD REQUIRING ONLY TWO PHOTOLITHOGRAPHIC STEPS", Y. Lebosq, et al., 1985 INTERNATIONAL DISPLAY RESEARCH CONFERENCE, pp. 34-36. This reference describes a process for forming scanning lines, data lines, TFTs, and pixel electrodes by using only two masks. Structural diagrams of an active matrix cell manufactured by the above process are illustrated in FIGS. 8A and 8B. Referring to FIG. 8A, the active matrix cell can be manufactured by only a first mask (non-hatched region) for forming data lines 10 and a pixel electrode 11 and a second mask (region of hatches inclined upward to the right) for forming a scanning line 12. FIG. 8B is a sectional view of the active matrix cell in FIG. 8A along the line VIIIB-VIIIB' thereof. Reference numerals 13a and 13b denote indium-tin-oxide (to be referred to as ITO hereinafter) conductive films; 14a and 14b, n-type amorphous silicon (to be referred to as n.sup.+ a-Si hereinafter); 15, amorphous silicon (to be referred to as a-Si hereinafter); 16, silicon oxide (SiO.sub.2) serving as a gate insulating film; and 17, an aluminum (to be referred to as Al hereinafter) wiring.
According to the above method, since only two masks are used, a parasitic TFT region 19 as an unnecessary TFT region in addition to a TFT region 18 serving as a necessary active element is undesirably formed under the scanning line 12, resulting in a decisive drawback. That is, when a channel length of the parasitic TFT region 19 is large, a conductivity is small and the display characteristics are not so adversely affected. However, when the channel length is decreased, the display characteristics are greatly degraded.
The three-mask process is a process wherein a TFT formation mask is added to the data line mask. For this reason, each TFT is limited to the necessary region and a parasitic TFT region can be eliminated, thus manufacturing an ideal structure.
FIGS. 9A to 9E are sectional views showing steps in manufacturing an active matrix cell according to the three-mask process, as described in "A 640.times.400 Pixel Active-Matrix LCD Using a-Si TFT's", T. Sunata, et al., IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. ED-33, No. 8, 1986, pp. 1218-1221. In this process, after a protective layer 21 is formed on a glass substrate 20, a transparent conductive film to be used for source and drain of the TFT, the data line, and the pixel electrode is deposited. In this case, an ITO film is used and patterned to form a transparent conductive film 22 (first mask), as shown in FIG. 9A. A phosphorus-doped n.sup.+ a-Si film 23 is selectively formed on the transparent conductive film 22 to form the source and and drain of the TFT, as shown in FIG. 9B. An a-Si film is deposited and patterned to form a TFT semiconductor region 24 (second mask). The a-Si film and the n.sup.+ a-Si film excluding the TFT region 24 are simultaneously removed, as shown in FIG. 9C. As shown in FIG. 9D, a silicon nitride (to be referred to as SiN.sub.x hereinafter) film 25 serving as a gate insulating film is deposited. Finally, a metal film, e.g., an Al film is deposited and patterned to obtain a scanning line 26 so as to include the gate electrode (third mask), as shown in FIG. 9E. The active matrix cell is formed using first to third masks in this process. Since the TFT thus formed has a gate electrode as the uppermost layer, this TFT is called a top gate staggered TFT. The drain and source of the TFT consist of lead lines for externally extracting currents and regions for effectively injecting only necessary carrier into the semiconductor. Although source and drain regions having a high impurity concentration (i.e., n.sup.+ or p.sup.+ region) formed by diffusion or the like is used in a transistor using crystalline silicon, an n.sup.+ a-Si film is used for source and drain to be deposited separately and additionally in a TFT using a-Si.
In the three-mask process, however, a photolithographic step and an a-Si film etching step are required between formation of the a-Si film serving as a TFT active region and formation of the SiN.sub.x film serving as the gate insulating film. An important interface for determining characteristics of a metal-insulator-semiconductor (MIS) field effect TFT tends to be contaminated. It is therefore difficult to form a high-mobility TFT with high reproducibility. In addition, the transparent conductive film 22 as the lowermost layer serves as the data line. When a display area is to be increased, the resistance of the transparent conductive film 22 must be reduced. However, the thickness of the transparent conductive film 22 cannot be extremely increased due to the following reason.
A film formed by normal plasma chemical vapor deposition (to be referred to as a PCVD hereinafter) used as a deposition method of the a-Si film has poor step coverage at the pattern edge and causes degradation of the TFT characteristics. In particular, when a step height increases, these affections become severe. In order to decrease a data line resistance in the above process, through holes must be formed in the SiN.sub.x film 25 existing on the entire surface and another metal wiring pattern must be formed to decrease the data line resistance. However, this process requires at least an additional mask for forming the through holes, thus losing the advantage of the three-mask process. Terminals must be extracted from the peripheral portion of the substrate to apply voltages to the data lines formed of the transparent conductive film 22 as the lowermost layer in the above process. For this reason, an insulating film should not exit on the peripheral transparent conductive film 22 portion. In order to manufacture an active matrix using the above mentioned active matrix cell, a metal mask must be prepared not to deposit the SiN.sub.x 25 on the peripheral transparent conductive film 22 portion during deposition of the SiN.sub.x 25 serving as a gate insulating film. The metal mask is aligned with the pattern on the substrate with a microscope. Poor mask alignment and poor contact between the metal mask and the substrate cause undesirable deposition of the insulating film under the metal mask.